What you’d do
Lead verification strategy and testbench architecture for semiconductor designs, writing complex test cases and debugging design bugs with design engineers. Full time. Found on the employer's careers page on Oct 18, 2026. Apply through the link.
You’ll need
- B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related
- 4–7 years hands-on DV experience in semiconductor/ASIC/SoC
- UVM/SystemVerilog methodology
- Verification planning and testbench architecture
- Constrained-random testing and functional coverage
Our summary of the listing. The full listing has the details.