Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

What you’d do

Perform synthesis, floorplanning, place and route, timing, and signoff checks for next-generation ASIC/SOC silicon used in Starlink space and ground systems. Requires a bachelor's degree and 5+ years of ASIC or physical design flow experience; extended hours and weekends as needed. Found on the employer's careers page on Sep 27, 2026. Apply through the link.