Principal Technical Program Manager, Annapurna Labs, Inc

What you’d do

Own the integrated schedule and critical path for multiple chip tape-outs through production ramp, and run the weekly chip status cadence across RTL/DV, physical design, packaging, power, and post-silicon teams. Track verification convergence and drive engineering response when it stalls. Full-time in Austin, Texas. Found on the employer's careers page on Oct 16, 2026. Apply through the link.

You’ll need

• 10+ years managing complex technology projects
• Chip development lifecycle knowledge
• RTL verification milestones
• Physical design convergence, DFT, timing closure