ASIC Technical Leader- RTL

What you’d do

Lead structural and functional test, diagnostic features, IP development and test access for networking silicon, working with front-end RTL and backend physical design teams. Full time in San Jose. Found on the employer's careers page on Oct 19, 2026. Apply through the link.

You’ll need

• 10+ years ASIC digital design experience
• Verilog/System Verilog coding
• Front-end tools: simulators, linting, CDC, synthesis, formal verification
• Interface protocols such as AMBA (AXI, APB, AHB), JTAG
• Memory test experience