Foundation IP Design Verification Intern (Summer 2027)

What you’d do

Intern verifies Foundation IP circuits and logic using SPICE and Verilog simulation, supports formal verification and post-silicon debug, and writes scripts to automate VLSI design and reporting tasks. Full-time summer internship in Santa Clara, California. Found on the employer's careers page on Oct 21, 2026. Apply through the link.

You’ll need

• At least a sophomore at application
• Pursuing Bachelor's, Master's, or PhD in EE, CS, or related
• Overall GPA of at least 3.0
• SPICE and Verilog simulation
• Scripting and CAD tools