Senior ASIC Physical Design Engineer, Netlisting

What you’d do

Drive physical design of high-frequency, low-power CPUs, GPUs, and SoCs at block, cluster, or full chip level, focusing on netlist work like equivalence checking, clock domain crossing checks, and logic synthesis. Also support timing convergence, timing constraints, and ECO implementation. Full time. Found on the employer's careers page on Sep 29, 2026. Apply through the link.