ASIC Engineering Technical Leader

What you’d do

Lead the full physical design flow for advanced ASIC/SoC chips including floorplanning, placement, and signoff to ensure first-pass silicon success. Innovate design methodologies and automate flows using TCL/Python. Full-time in San Jose. Found on the employer's careers page on Oct 23, 2026. Apply through the link.

You’ll need

• Bachelor's plus 8 years or Master's plus 6 years or PhD plus 3 years experience
• Experience in ASIC/SoC physical design in advanced tech nodes
• Hands-on full physical design flow at block or chip level