Senior ASIC RTL Engineer

What you’d do

Member of the Silicon One development organization, working with front-end RTL and backend physical design teams to produce high-quality Design for Test RTL for networking silicon. Full time. Found on the employer's careers page on Oct 19, 2026. Apply through the link.

You’ll need

• Bachelor's or Master's in Electrical or Computer Engineering
• 7+ years of experience
• Verilog/SystemVerilog coding
• Front-end tools: simulators, linting, CDC, synthesis, formal verification