ASIC DFT Emulation Technical Lead

What you’d do

Lead DFT emulation strategy for Silicon One, architecting emulation environments and validating scan, MBIST, and JTAG architectures on Palladium, Veloce, or Zebu. Run pre-silicon test plans and support post-silicon pattern conversion with RTL, physical design, and ATPG teams. Full time. Found on the employer's careers page on Oct 18, 2026. Apply through the link.

You’ll need

• Bachelor's + 8 years, Master's + 6, or PhD + 3 years experience
• Emulation experience on Palladium, Veloce, or Zebu
• Emulation compilation and debug experience
• Verilog and SystemVerilog experience