ASIC Design Verification Engineer

What you’d do

Builds and maintains ASIC design verification environments, writes and runs test plans for block and cluster level chips, and runs gate level simulations to qualify RTL designs. Full time in San Jose, California. Found on the employer's careers page on Oct 17, 2026. Apply through the link.

You’ll need

• Bachelor's in computer, electrical or electronics engineering
• 5+ years relevant technical experience (or master's + 3)
• ASIC design and verification experience
• SystemVerilog or UVM methodology