ASIC Link Modeling Technical Leader

What you’d do

Develop system-level behavioral models and link simulations for silicon photonics systems, covering high-speed SerDes, optical DSP, and die-to-die interfaces. Lead link budget analysis, transceiver architecture optimization, and correlate pre-silicon models with lab measurements. Full time. Found on the employer's careers page on Oct 18, 2026. Apply through the link.

You’ll need

• Bachelor's + 12 years related experience, or Master's + 8, or PhD + 5 in ASIC link modeling
• Proficiency in Python, C/C++, and MATLAB
• ASIC link modeling experience
• Behavioral model development and link simulation
• IBIS-AMI modeling