VLSI Design Verification Masters Level Intern

What you’d do

Intern on the HPE Slingshot interconnect team, developing SystemVerilog and UVM testbench components for a switch or NIC ASIC verification project. Full-time role working with architects, logic designers, and verification engineers. Found on the employer's careers page on Oct 21, 2026. Apply through the link.

You’ll need

• Pursuing Master's in EE, Computer Engineering, CS, or related
• Coursework in digital design and computer architecture
• Experience with object-oriented programming
• ASIC or VLSI experience
• SystemVerilog and UVM (learned on the job)