Sr. PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning

What you’d do

Define and deploy STA/EMIR signoff and physical design methodologies for ML accelerator chips in advanced nodes, optimize CAD flows for timing, PPA and turnaround, and work with EDA vendors and RTL, physical design, package and DFT teams. Full-time in Austin, Texas. Found on the employer's careers page on Oct 20, 2026. Apply through the link.

You’ll need

• 7+ years ASIC implementation, synthesis, STA and physical design
• Deep sub-micron nodes 16nm or smaller
• Bachelor's in Electrical Engineering or related field
• TCL and Python scripting
• Multiple power islands and power gating knowledge