Static Timing Analysis Design Engineer / Physical Design

What you’d do

Own end-to-end timing constraints and static timing analysis for complex SoC designs, from early constraint development through final timing signoff. Work with frontend, IP and DFT teams to debug failing paths and provide automated and manual timing ECOs. Found on the employer's careers page on Oct 21, 2026. Apply through the link.

You’ll need

• Bachelor's or Master's in Electrical/Electronics Engineering
• 3-6 years ASIC/SoC timing analysis experience
• Strong knowledge of Synopsys STA tools
• Strong communication skills
• Experience in high-reliability SoCs