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Digital Physical Design (P&R) Intern

NXP SemiconductorsChandler, AZ

Posted Jul 13, 2026

What you’d do

Intern will support digital backend physical design flow from synthesis to GDS2 using Cadence tools, run experiments on RTL implementations, study tool manuals, and suggest flow improvements. Full-time internship in Chandler office. Found on the employer's careers page on Oct 21, 2026. Apply through the link.

You’ll need

  • Pursuing Master's in Electrical Engineering with digital design focus
  • Experience with digital backend flow is a strong plus
  • Willing to relocate to Phoenix Metro area
  • Minimum 3 days per week in Chandler office

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