Sr. Staff CAD- ASIC Design Verification Agentic Workflow

What you’d do

Lead development of next-generation agentic design verification workflows and add-on tools as a key CAD member of Central Engineering. Involves defining the organization's design infrastructure, methodology, and workflows. Found on the employer's careers page on Oct 20, 2026. Apply through the link.

You’ll need

• BS/MS in Electrical Engineering, Computer Engineering, or related field
• SystemVerilog UVM and SVA expertise
• Functional coverage and constrained-random verification
• Simulation-based and formal verification experience
• Emulation/FPGA prototyping experience