Senior ASIC DFT DV Engineer (Hybrid)

What you’d do

Plan and build test benches to verify Design-for-Test architecture for silicon, own MBIST methodology across the Silicon One portfolio, and architect reusable hierarchical verification infrastructure. Full-time hybrid role in San Jose, California. Found on the employer's careers page on Oct 17, 2026. Apply through the link.

You’ll need

• Bachelor's in Electrical Engineering or equivalent
• 7+ years experience (or Master's with 4+ years)
• Test planning from complex design specifications
• Debugging with DVE/Verdi
• Memory architectures (SRAM, DRAM) and failure modes