Design Verification Engineering Intern - MS/PhD

What you’d do

Intern will develop verification plans, test benches, and simulations for mixed-signal circuits, run coverage regressions, track verification status, and work with regression tools and RTL/Gates+SDF. Role involves constrained-random stimulus and chip-level timing verification. Found on the employer's careers page on Oct 23, 2026. Apply through the link.

You’ll need

• Pursuing graduate degree in Electrical or Computer Engineering
• 3.0/4.0 GPA or higher
• Strong verbal and written communication skills
• Ability to build relationships with stakeholders