Pre-Silicon Verification Engineer

What you’d do

Develop verification environments and tests in System Verilog and UVM for clock generator IPs such as PLL and FLL, perform functional verification against microarchitecture specs, and debug pre-silicon issues. Full time role in Hillsboro, Oregon. Found on the employer's careers page on Oct 10, 2026. Apply through the link.

You’ll need

• System Verilog
• UVM
• Functional verification of clock generator IPs (PLL, FLL)
• Debug and root-cause pre-silicon issues
• Cross-functional collaboration with architects and RTL/analog teams