VLSI Logic Design Intern

What you’d do

Intern on the HPE Cray Slingshot team assisting with VLSI and RTL design in System Verilog, writing assertions and running formal verification, analyzing coverage, and scripting in Python, TCL, or Perl. Full time. Found on the employer's careers page on Oct 21, 2026. Apply through the link.

You’ll need

• Working toward Bachelor's or Master's in Electrical Engineering, Computer Engineering or equivalent
• Experience with System Verilog for synthesis (ASIC or FPGA)
• System Verilog Assertions and formal verification
• Scripting in Python, TCL, or Perl
• Detail-oriented and self-driven