Design Verification Engineer - APS

What you’d do

Develop verification strategies and build scalable UVM-based testbenches using UVM, Verilog, SystemVerilog, and Python. Drive functional and code coverage to closure in this electrical engineering role. Found on the employer's careers page on Oct 22, 2026. Apply through the link.

You’ll need

• Bachelor's degree in electrical engineering
• 8+ years of experience
• Experience with UVM, Verilog, SystemVerilog, Python
• Developing verification strategies
• Building scalable UVM-based testbenches