Design Engineer I

What you’d do

Define and implement SoC-level DFT architecture for large, complex chip designs, covering SCAN, ATPG, MBIST, BSCAN and iJTAG, plus DFT insertion, verification and coverage analysis. Support pre-silicon sign-off and post-silicon debug alongside RTL, verification and physical design teams. Full time. Found on the employer's careers page on Oct 18, 2026. Apply through the link.

You’ll need

• BS degree
• 3+ years hands-on SoC DFT experience
• Expertise in SCAN, ATPG, MBIST
• Pre-silicon validation and post-silicon debug experience
• Cross-functional collaboration skills