Senior EDA Tools Hardware Engineer

What you’d do

Develop and maintain transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, register files, and compiler-generated macros. Work with circuit, memory design, and STA teams on automation and model validation. Full time in Santa Clara, CA. Found on the employer's careers page on Oct 9, 2026. Apply through the link.

You’ll need

• SPICE-based characterization experience
• Liberty model generation
• Custom macro timing behavior knowledge
• Synopsys NanoTime
• Cadence Liberate