Sr. PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning

What you’d do

Define and deploy physical design and verification methodologies (RTL2GDS) for ML accelerator chips in advanced nodes, optimize CAD flows for PPA and turnaround, and work with EDA vendors and RTL, PD, package, and DFT teams. Full-time in Austin, Texas. Found on the employer's careers page on Oct 20, 2026. Apply through the link.

You’ll need

• 7+ years ASIC implementation, synthesis, STA, physical design
• Deep sub-micron nodes 16nm or smaller
• Bachelor's in Electrical Engineering or related field
• Power islands and power gating implementation
• Scripting in TCL, Python