ASIC Design Verification Engineer, Technical Leader

What you’d do

Maintain and enhance design verification environments, build test benches with scoreboards, agents, sequencers and monitors, write test plans and debug regression failures to verification closure. Full time in San Jose, California. Found on the employer's careers page on Oct 18, 2026. Apply through the link.

You’ll need

• Bachelor's with 8+ years or Master's with 6+ years relevant experience
• System Verilog experience
• UVM methodology experience
• Verifying complex blocks, cluster, or top level for ASIC/SoC