ASIC Technical Leader- CAD

What you’d do

Own end-to-end DFT flow architecture and build scalable CAD infrastructure across the design cycle, from RTL and insertion to ATPG, simulation, and reporting. Develop LSF-based regression frameworks and apply AI-driven automation to log analysis and debug, working with RTL, Physical Design, and Validation teams. Found on the employer's careers page on Oct 17, 2026. Apply through the link.

You’ll need

• 8+ years in CAD or test automation for semiconductor designs
• AI/ML applied to EDA workflows
• EDA DFT toolchain experience (Synopsys TestMAX, VCS, Tessent)
• DFT flow architecture and regression frameworks
• Cross-functional collaboration with RTL and physical design teams