Senior Static Timing Analysis (STA) Engineer

What you’d do

Perform SOC-level static timing analysis and optimization, generate and verify timing constraints, and resolve timing violations at chip or block level. Develop optimized clock networks and timing methodologies while working with clocking, DFT, and logic design teams. Full time in Phoenix, Arizona. Found on the employer's careers page on Oct 6, 2026. Apply through the link.

You’ll need

• SOC-level static timing analysis (STA) experience
• Timing constraints generation and verification
• Clock network design and optimization
• PVT condition definition for timing analysis
• Experience with physical design flows