EngineeringOn site
Principal Design Engineer
CadenceSan Jose, CA
$140,000–260,000/yr
Posted Oct 9, 2026
What you’d do
Lead a team implementing and verifying Palladium and Protium SOCs, covering RTL synthesis, floor planning, clock tree building, timing closure, IR drop and physical verification through tape out. Full time in San Jose. Found on the employer's careers page on Oct 18, 2026. Apply through the link.
You’ll need
- BS in Electrical Engineering + 7 years, or MS + 5, or PhD + 1
- Experience with Innovus, Tempus, QRC, Voltus, Pegasus
- Experience with 5nm, 3nm and 2nm nodes
- RTL synthesis and floor planning
- Team leadership
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