Group Director, Design Engineering - Front End

What you’d do

Lead Front End Design projects and guide a team of RTL design engineers. Define microarchitectural features for IPs and subsystems, write and optimize RTL code, and oversee pre-silicon verification. Full time in Austin. Found on the employer's careers page on Oct 18, 2026. Apply through the link.

You’ll need

• 10+ years Front End design and/or verification
• BS/MS in Engineering or Computer Sciences
• Experience leading and managing complex engineering projects
• IP creation and/or SoC and IP integration experience
• RTL in Verilog, SystemVerilog, or VHDL