Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging

What you’d do

Perform package-level signal and power integrity simulations for 2.5D, 3D-IC, fan-out, and interposer architectures, including S-parameter extraction, eye diagrams, and PDN analysis. Full-time role coordinating with SoC and board design teams on package stack-up and interconnect modeling. Found on the employer's careers page on Sep 30, 2026. Apply through the link.