ASIC Design Engineer

What you’d do

Design ASIC blocks from micro-architecture specs through Verilog/SystemVerilog implementation, write functional coverage and SVA, and work with physical design and verification teams on timing closure. Full time in Sunnyvale, with mentoring of new grads and interns. Found on the employer's careers page on Oct 20, 2026. Apply through the link.

You’ll need

• Bachelor's in Electrical Engineering
• 4+ years of relevant experience
• Verilog or SystemVerilog
• Functional coverage/SVA
• Timing closure and RTL timing fixes