Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging

What you’d do

Lead the full package layout cycle for AI silicon, from die floor planning and bump assignment through RDL routing, substrate design, verification, and tape out. Work on advanced packaging such as 2.5D interposers, 3D-IC, and fan-out wafer-level packaging. Full-time in Tempe, Arizona. Found on the employer's careers page on Sep 30, 2026. Apply through the link.