Static Timing Analysis Design Engineer / Physical Design

What you’d do

Perform end-to-end static timing analysis and timing constraints development for advanced SoC designs. Collaborate with implementation engineers from synthesis to timing closure, debug timing paths, and provide timing ECOs in a full-time role in Austin. Found on the employer's careers page on Oct 23, 2026. Apply through the link.

You’ll need

• Bachelor's or Master's in Electrical/Electronics Engineering or related field
• 3-6 years of ASIC/SoC Timing Analysis experience
• Strong knowledge of Synopsys STA tools
• Experience with high-reliability SoCs
• Strong communication skills