Senior ASIC DFT DV Engineer (Hybrid)

What you’d do

Senior ASIC DFT verification role: plan and build SystemVerilog testbenches to verify design-for-test architecture for ATE screening, in-system test and diagnostics, working with design, verification and PD teams through implementation and post-silicon validation. Hybrid, full time in San Jose. Found on the employer's careers page on Oct 17, 2026. Apply through the link.

You’ll need

• Bachelor's in Electrical Engineering or equivalent
• 7+ years experience (or Master's with 4+)
• Test planning from complex design specifications
• SystemVerilog testbench development
• Debugging with DVE/Verdi