Principal DFT Engineer (Silicon Engineering)

What you’d do

Lead DFT architecture implementation for next-generation Starlink ASICs, including scan insertion, memory and logic BIST, and ATPG pattern generation using Siemens Tessent tools. Role also covers gate-level simulation, post-silicon validation support, and test automation scripting; extended hours and weekends may be required. Found on the employer's careers page on Sep 27, 2026. Apply through the link.