ASIC Design Engineer (Silicon Engineering)

What you’d do

Design ASICs and FPGAs for Starlink, implementing complex SoC blocks and integration in Verilog/SystemVerilog, optimizing for power, performance and area, and supporting lab bring-up and validation. Found on the employer's careers page on Oct 10, 2026. Apply through the link.

You’ll need

• Bachelor's in Electrical Engineering, Computer Engineering, Computer Science, or Physics
• 1+ years of RTL design using SystemVerilog, Verilog or VHDL
• ASIC/FPGA system integration experience
• Proficiency in Python, C/C++, and Bash