IC design Implementation and SignOff Architect, (STA SignOff)

What you’d do

Lead technical engagements with customers to drive adoption of Cadence's timing signoff and closure tools at advanced nodes, including STA, IR drop, and power/timing closure. Partner with R&D on tool enhancements and represent Cadence at industry forums. Full time. Found on the employer's careers page on Oct 18, 2026. Apply through the link.

You’ll need

• 15+ years IC design implementation and signoff experience
• BS/MS in Electrical Engineering, Computer Engineering, or related
• Advanced node STA & ECOs (3nm and below)
• Digital design fundamentals
• EDA tool ecosystems