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PCB Layout Engineer

Hewlett Packard EnterpriseSunnyvale, CA

Posted Oct 5, 2026

What you’d do

Layout and route backplanes and dense high-speed PCBs in Cadence Allegro, covering placement, routing, constraint table management and tape out. Full time in Sunnyvale, California. Found on the employer's careers page on Oct 21, 2026. Apply through the link.

You’ll need

  • Minimum 2 years of college or equivalent
  • Minimum 2 years' PCB layout experience
  • Cadence Allegro layout, DRC and post process
  • Cadence Constraint Manager
  • High-speed, high-density PCB design and DFM/DFX

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