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AMS Digital Design Engineer Intern

Astera LabsSan Jose, CA

$35–55/hr

Posted Oct 13, 2026

What you’d do

Digital RTL design intern on the San Jose design team, translating specifications into synthesizable RTL, debugging digital logic, and helping integrate complex ASICs alongside verification, synthesis, and physical design teams. Found on the employer's careers page on Oct 21, 2026. Apply through the link.

You’ll need

  • Digital logic design and RTL development skills
  • ASIC design and integration coursework or experience
  • Currently enrolled student (education level sets pay range)
  • On-site in San Jose, CA

Our summary of the listing. The full listing has the details.

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