ASIC/SOC DFT Engineer (Silicon Engineering)

What you’d do

Develop and verify Design for Test (DFT) fabrics and scan insertion for next-generation ASICs used in Starlink satellites and ground infrastructure. Involves ATPG analysis, gate-level simulation, and collaboration with physical design and manufacturing teams; extended hours and weekends may be required. Found on the employer's careers page on Sep 27, 2026. Apply through the link.