Principal ASIC Design Engineer

What you’d do

Architect and implement complex ASIC modules for high performance networking chips, writing micro-architecture specs and RTL in Verilog or SystemVerilog, meeting power and timing targets, and mentoring junior engineers. Full time. Found on the employer's careers page on Oct 21, 2026. Apply through the link.

You’ll need

• Bachelor's in Electrical Engineering
• 15+ years relevant experience
• Verilog or SystemVerilog
• ASIC architecture and RTL implementation
• Timing closure with physical design team