Senior Physical Design and Timing Engineer

What you’d do

Drive physical design and timing for high-frequency, low-power CPUs, GPUs, LPUs, and SoCs at block, cluster, or full chip level. Handle frontend and backend implementation from RTL to GDS2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation. Full time. Found on the employer's careers page on Sep 29, 2026. Apply through the link.