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Digital Design Engineering Intern

Astera LabsSan Jose, CA

$35–55/hr plus $500/week housing stipend

Posted Sep 8, 2026

What you’d do

Work on digital design projects involving ASIC and digital hardware blocks, including RTL implementation, simulation, synthesis, and design-quality checks. Gain experience with Verilog/SystemVerilog and collaborate with engineers on design verification and handoff. Found on the employer's careers page on Oct 22, 2026. Apply through the link.

You’ll need

  • Enrollment in electrical/computer engineering or related degree
  • Experience with digital logic or ASIC/FPGA design
  • Knowledge of Verilog or SystemVerilog
  • Ability to work on RTL implementation and simulation

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