ASIC DFT STA Engineer

What you’d do

Work as an ASIC DFT STA Engineer in Silicon One development, focusing on timing constraints, DFT and quality processes through implementation and validation phases, with some physical design signoff tasks. Full-time position in San Jose, CA. Found on the employer's careers page on Oct 22, 2026. Apply through the link.

You’ll need

• Bachelor's + 7 years experience or Master's + 4 years or PhD + 1 year
• Experience with RTL design, CDC/RDC, conformal verification, SDC development
• Experience in timing constraint development and verification