Sr. ASIC Design Engineer

What you’d do

Design ASIC blocks from micro-architecture specs through RTL implementation in Verilog/SystemVerilog, write functional coverage and SVA, and work with physical design and verification teams on timing closure and validation. Full time in Roseville, California. Found on the employer's careers page on Oct 21, 2026. Apply through the link.

You’ll need

• Bachelor's in Electrical Engineering
• 5+ years relevant experience
• Verilog or SystemVerilog
• Functional coverage/SVA
• RTL timing closure