SOC Top Level Physical Design Engineer, Annapurna Labs

What you’d do

Drive full chip floorplan, placement, integration, PV signoff and tapeout, and perform DRC, LVS and PERC verification using EDA tools. Full-time role in Austin, Texas, also involving foundry interface and mentoring junior engineers. Found on the employer's careers page on Sep 30, 2026. Apply through the link.