Senior Software Architect

What you’d do

Design and enhance the Xcelium RTL/logic simulator and timing constraints verification, including graph algorithms for SDC constraints and C/C++ performance tuning. Lead junior engineers and collaborate with a global team; full time. Found on the employer's careers page on Oct 18, 2026. Apply through the link.

You’ll need

• MS in CS or EE with 12+ years, or PhD with 10+ years
• 10+ years EDA software development
• RTL/logic simulation and SDC constraints
• Timing analysis and path exceptions in STA
• C/C++ performance optimization