EngineeringOn site
Sr Principal Engineer -SIPI
CadenceSan Jose, CA
$154,000–286,000/yr
Posted Oct 18, 2026
What you’d do
Design and verify signal and power integrity for test chip packages and evaluation boards, build channel models for R&D designers, and support customers on SI/PI questions. Includes lab debug of test chips and customer ASICs. Found on the employer's careers page on Oct 19, 2026. Apply through the link.
You’ll need
- M.S. or Ph.D. in electrical engineering or similar
- 3+ years experience, preferably high speed SerDes and PHYs
- Simulation-to-lab measurement correlation experience
- PCB and FCBGA design rules knowledge
- S-parameter and IBIS-AMI link simulation
Our summary of the listing. The full listing has the details.