ASIC DFT Engineering Technical Leader

What you’d do

Lead ASIC Design-for-Test efforts in Silicon One chip development, collaborating with RTL and physical design teams to define DFT requirements and support implementation through post-silicon validation. Full-time in San Jose, CA. Found on the employer's careers page on Oct 22, 2026. Apply through the link.

You’ll need

• Bachelor's in Electrical or Computer Engineering
• 8+ years experience or Master's + 6 years or PhD + 3 years
• Experience with ASIC DFT and chip architecture
• Ability to work with ATE engineers
• Full-time schedule