Senior ASIC Design Verification Engineer - Slingshot

What you’d do

Perform all phases of pre-silicon design verification, including methodology, test-plan and testbench development, coverage closure, and sign-off reviews. Build SystemVerilog and UVM testbench components and triage regression failures. Hybrid role, about 2 days per week in an HPE office. Found on the employer's careers page on Oct 20, 2026. Apply through the link.

You’ll need

• Bachelor's or Master's in EE, Computer Engineering, CS, or equivalent
• 10+ years in VLSI design, verification, or implementation
• Expert knowledge of SystemVerilog
• Expert knowledge of OVM or UVM
• Hybrid, 2 days/week in office